Several different computer I/O interconnect standards are developed for connecting computer elements. One of the most popular computer I/O interconnect standards over the years is the Peripheral Component Interconnect (PCI) standard. The PCI allows the bus to act like a bridge, which isolates a local processor bus from the peripherals, allowing a Central Processing Unit (CPU) of the computer to run must faster. Recently, a successor to PCI has been popularized, termed PCI Express (or, simply PCIe). The PCIe provides higher performance, increased flexibility and scalability for next-generation systems while maintaining software compatibility with existing PCI applications.
Compared to legacy PCI, the PCIe Express protocol with three layers (a transaction layer, a data link layer and a physical layer) is considerably more complex. In the transaction layer, PCIe implements split transactions with request and response separated by time, allowing the link to carry other traffic while the target device gathers data for the response. The data link layer sequences the Transaction Layer Packets (TLPs) that are generated by the transaction layer, ensures reliable delivery of TLPs between two endpoints via an acknowledgement protocol that explicitly requires replay of unacknowledged/bad TLPs, and initializes and manages flow control credits. The physical layer specification is divided into a two sublayers, corresponding to electrical and logical specifications.
In a PCIe system, a root complex device connects the processor and memory subsystem to the PCIe switch fabric comprised of one or more switch devices. In PCIe, a point-to-point architecture is used. Similar to a host bridge in a PCI system, the root complex generates transaction requests on behalf of the processor, which is interconnected through a local I/O interconnect. Root complex functionality may be implemented as a discrete device, or may be integrated with the processor. A root complex may maintain more than one PCIe port and multiple switch devices can be connected to the ports on the root complex or cascaded.
An existing solution Non-Transparent Bridge (NTB) is described that uses memory redirection methods when multiple hosts are connected using the non-transparent ports of a PCIe switch. Normally, the NTB is presented with two back-to-back endpoints, each endpoint handles memory map and translation function of one direction, so the NTB can do the memory redirection function in two ways between two hosts connected through the NTB.
FIG. 1 is a diagram illustrating a memory mapping system for mapping the physical address of host 1 to physical address of host 2 through an endpoint of the NTB.
In FIG. 1, the left endpoint LE of the NTB has 6 Base Address Registers (BARs) LEBar 0˜LEBar 5 and supports 6 addresses mapping of 32 bits address. For example, the LEBar (left end base address register) 0 and the LEBar 1 map the physical address 0x00000000˜0x10000000 of host 1 to the physical address 0x30000000˜0x40000000 of host 2, the LEBar 2 and the LEBar 3 map the physical address 0x20000000˜0x40000000 of host 1 to the physical address 0x00000000˜0x20000000 of host 2, and the LEBar 4 and the LEBar 5 map the physical address 0x50000000˜0x70000000 of host 1 to the physical address 0x50000000˜0x70000000 of host 2.
FIG. 2 is a diagram illustrating a memory mapping system for mapping the physical address of host 2 to physical address of host 1 through an endpoint of the NTB. In FIG. 2, the right endpoint RE of the NTB has 6 BARs, REBar 0˜REBar 5, and supports 6 addresses mapping of 32 bits address. Similar to FIG. 1, the REBar 0 to REBar 5 map the physical address of host 2 to the physical address of host 1. Each PCIe endpoint has only 6 Bars and supports maximum 6 addresses mapping of 32 bits address or 3 addresses mapping of 64 bits address, and therefore, the number of BARs is the most critical resource of the NTB function.